The structure of CPLD is based on Product-Term and can be divided into three parts: Function Block, FastCONNECT II SwitchMatrix, and I/O Control Module. Each Function Block includes programmable logic array, product-term allocator, and 18 macrocells. The FastCONNECT II SwitchMatrix is responsible for signal transmission and connects all the Function Blocks. The I/O Control Module is responsible for controlling the electrical characteristics of input and output, such as setting open-drain output, tri-state output, etc. The signals I/O/GCK, I/O/GSR, and I/O/GTS in Figure 1 are global clock, global reset, and global output enable signals, which are connected to each Function Block in CPLD through dedicated wires. The delay of these signals to each Function Block is the same and the shortest. Macrocell is the basic structure of CPLD, and it is used to implement basic logic functions. The product-term array is actually an AND-OR array, and each crosspoint is programmable. If it is conducting, it implements "AND" logic, and together with the product-term allocator, it completes the combinational logic.
Principle of CPLD Logic Implementation
Taking a simple circuit as an example, this will explain how CPLD utilizes the above structure to implement logic. The circuit is shown in Figure 2.
Assuming the output of the combinational logic is f, then f＝（A十B）* C *（!D）＝A * C*!D＋B*C *!D CPLD will implement the combinational logic f in the manner shown in Figure 3.
A, B, C, and D are input into the interconnect matrix after being fed into the pins of the PLD chip. Internally, there will be 8 outputs for A, A, B, B, C, C, D, and D. Each cross in Figure 3 represents a connection, so we have: f = fl + 12 = (A * C * !D) + (B * C * !D), thus implementing the combinational logic. In Figure 2, the implementation of the D flip-flop is relatively simple, directly utilizing the programmable D flip-flop in the macro units . The clock signal CLK is input through the I/O pin and enters the chip's internal global clock dedicated channel, directly connected to the clock terminal of the programmable flip-flop. The output of the programmable flip-flop is connected to the I/O pin, and the result is output to the chip pin. In this way, CPLD completes the functionality of the circuit shown in Figure 2. All of these steps are automatically performed by the software and do not require human intervention.
The circuit in Figure 2 is a very simple example that can be completed with just one macro unit. However, for a complex circuit, it is not possible to achieve it with just one macro unit. In this case, multiple macro units need to be connected through parallel expansion terms and shared expansion terms, and the output of the macro unit can also be connected to the interconnect matrix and used as the input of another macro unit. This way, CPLD can implement more complex logic.
This type of CPLD based on product terms is mostly manufactured by E2PROM and Flash technology, and it can work as soon as it is powered on without the need for other chips to cooperate.